The present invention relates to the design and testing of semiconductor integrated circuits for potential fabrication faults. More specifically, the present invention relates to a method and apparatus of estimating state-dependent gate leakage.
Following fabrication, semiconductor integrated circuits such as complimentary metal-oxide semiconductor (CMOS) circuits are tested for a variety of potential fabrication faults. One type of test is known as xe2x80x9cstatic current testingxe2x80x9d. Static current testing is based on an assumption that a fault-free CMOS circuit draws very little supply current in a steady state. This current is known as xe2x80x9cleakagexe2x80x9d current. Certain manufacturing faults on an integrated circuit cause unwanted shorts within the devices fabricated on the integrated circuits. Under certain test conditions, these shorts can cause an increase in the current drawn by the integrated circuit. A faulty integrated circuit often draws current that is several orders of magnitude greater than that drawn by a non-faulty integrated circuit. Therefore, the leakage current drawn by an integrated circuit under certain test conditions can be used to indicate the presence of a manufacturing defect in the circuit.
Static current testing is performed by applying test vectors to the integrated circuit and making one or more current measurements during a quiescent state of the circuit. A test vector is typically applied to the circuit by serially shifting the test vector into the circuit through a chain of xe2x80x9cscannablexe2x80x9d elements and then clocking the circuit. The test vectors that are used for static current testing contain vectors that will put the circuit into a low drain current (IDD) state. Static current testing is often referred to as IDDQ testing.
Once the circuit is in the desired state, the circuit is xe2x80x9cstrobedxe2x80x9d near the end of a clock cycle. That is, a snapshot of the circuit is taken, and the status of selected pins and nets is recorded along with the stability of the circuit. The strobe point for each test vector is usually the last time unit in the clock cycle. If the state of the circuit at a particular strobe point is such that a defect-free chip in that state would not draw supply current, then the test vector and the resulting test patterns obtained at that strobe point can be successfully used for IDDQ testing.
There are several contributors to leakage current that is drawn when the circuit is in a low-current drawing state. These contributors include sub-threshold (device-off) leakage, thermal and tunneling junction leakage, and gate-or-oxide leakage. Previously, gate or oxide leakage was largely ignored since it accounted for only a small amount of the total leakage current. Also, Gate leakage was difficult to estimate since it is state-dependent. Gate leakage flows only when a device is xe2x80x9cONxe2x80x9d. If a device is xe2x80x9cOFFxe2x80x9d then the gate leakage is zero. Without knowing the state of each transistor in a design, an accurate gate leakage estimate for a design is not possible.
With low leakage devices, such as wireless and hand-held devices, gate leakage is becoming a greater factor in the total leakage current within the device. For example, gate leakage can account for about 25% of the total leakage current in a low-leakage device. Therefore, gate or oxide leakage can no longer be ignored as it has in the past. However, conventional simulation tools in the market today are not capable of accurately simulating gate leakage. Although some conventional tools are capable of estimating total possible NMOS and PMOS gate leakage, they are not capable of taking into account the state-dependency of these leakage""s. Therefore, conventional tools are not accurate and cannot be used as a means for generating an estimate that can be used for screening defective parts due to high gate leakage.
Improved methods and apparatus for estimating gate leakage are desired.
One embodiment of the present invention is directed to a method of estimating gate leakage of an integrated circuit design having a plurality of transistors. The method includes simulating an operating state of the integrated circuit design and estimating the gate leakage as a function of the states of the transistors in response to the simulated operating state.
Another embodiment of the present invention is directed to a method of estimating gate leakage of an integrated circuit design having at least one element. The method includes simulating an operating state of the integrated circuit design, identifying logic states at inputs to the element in response to the operating state, and producing a gate leakage estimate based on the logic states at the inputs to the element.
Yet another embodiment of the present invention is directed to an integrated circuit technology library. The library includes a cell library definition for each of a plurality of elements in the library. Each cell library definition includes a list of inputs to the element, a list of each transistor in the element, a gate area for each of the transistors in the element, a gate leakage per unit area for each of the transistors in the element, and a gate leakage estimate for each combination of logic states at the inputs to the element. The gate leakage estimate is based on the gate area and the gate leakage per unit area of each of the transistors in the element that are in an ON state for that combination of logic states.